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19-0555; Rev 2; 10/07
KIT ATION EVALU BLE AVAILA
24-Output PWM LED Drivers for Message Boards
General Description Features
o 24 LED Current Sink Outputs (Three Banks of Eight Outputs) o 48 LED Drive Option When Multiplexing o 33MHz Clock Supports Up to 63 Frames per Second of Video o Constant Output Current Calibration from 6mA to 30mA in 256 Steps o EZCascadeTM Interface Simplifies Multiple Driver Cascading Without External Buffers o 12-Bit or 14-Bit Individual PWM LED Intensity Controls o 7-Bit or 5-Bit Panel PWM-Intensity Control o +3V to +7V LED Power Supply o +3.0V to +3.6V Logic Supply o Open-Circuit LED Fault Detection o Optional Watchdog Timer Blanks Display if Interface Fails o Standard -40C to +125C Operating Temperature Range
MAX6974/MAX6975
The MAX6974/MAX6975 precision current-sinking, 24-output PWM LED drivers drive red, green, and blue LEDs for full-color graphic message boards and video displays. Each output has an individual 12-bit (MAX6974) or 14-bit (MAX6975) PWM-intensity (hue) control and 7-bit (MAX6974) or 5-bit (MAX6975) global PWM intensity (luminance) control. The MAX6974/MAX6975 feature a high-speed, fully buffered cascadable serial interface, open-circuit LED fault detection circuitry, as well as a watchdog timer. The driver has three banks of eight outputs, with each bank intended to drive a different color in RGB applications. The full-scale current for each bank of eight outputs is adjustable from 6mA to 30mA in 256 steps (0.3125% per step) to calibrate each color. The MAX6974/MAX6975 can optionally multiplex by using outputs MUX0 and MUX1, which each drive an external pnp transistor. Multiplexing doubles the MAX6974/MAX6975 drive capability to 48 LEDs. The MAX6974/MAX6975 operate from a 3.0V to 3.6V power supply. The LED power supply can range from 3V to 7V. The LED drivers require only 0.8V headroom above the LEDs' forward-voltage drop. Using a separate LED supply voltage for each LED minimizes power consumption. The serial interface uses differential signaling for the high-speed clock and data signals to reduce EMI and improve signal integrity. The MAX6974/MAX6975 buffer all interface signals to simplify cascading devices in modules that use a large number of drivers. An internal watchdog timer, when enabled, automatically clears the pixel-data registers and blanks the display if any of the signal inputs fail to toggle within 40ms. The MAX6974/MAX6975 are available in 40-pin TQFN packages and operate over the -40C to +125C temperature range. Refer to the MAX6972/MAX6973 data sheet for a 16-output, 11mA to 55mA software-compatible device.
EZCascade is a trademark of Maxim Integrated Products, Inc.
Ordering Information
PART MAX6974ATL+ MAX6975ATL+ TEMP RANGE -40C to +125C -40C to +125C PINPACKAGE 40 TQFN-EP* 40 TQFN-EP* PKG CODE T4066-3 T4066-3
*EP = Exposed paddle. +Denotes a lead-free package.
Pin Configuration
LOADO DOUT+ CLKO+ DOUTCLK0MUX1 G7 G6 G5 20 G4 19 G3 EP* 18 G2 17 G1 16 G0 15 R7 14 R6 13 R5 12 R4 11 R3 1 MUX0 2 CLKI+ 3 CLKI4 DIN+ 5 DIN6 LOADI 7 I.C. 8 R0 9 R1 10 R2
TOP VIEW
30 29 28 27 26 25 24 23 22 21 AGND 31 B7 32 B6 33 B5 34 B4 35 B3 36 B2 37 B1 38 B0 39 VDD 40
Applications
LED Video Display Panels LED Message Boards Variable Message Signs (VMS) Signs Graphic Panels
Typical Operating Circuit appears at the end of data sheet.
MAX6974ATL/ MAX6975ATL +
TQFN-EP
*EP = EXPOSED PADDLE.
________________________________________________________________ Maxim Integrated Products
VDD
1
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24-Output PWM LED Drivers for Message Boards MAX6974/MAX6975
ABSOLUTE MAXIMUM RATINGS
(All voltages with respect to GND.) VDD ........................................................................-0.3V to +4.0V R0-R7, G0-G7, B0-B7, MUX0, and MUX1 ...........-0.3V to +8.0V All Other Pins..............................................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70C) 40-Pin TQFN (derate 37mW/C over +70C) .............2963mW Operating Temperature Range .........................-40C to +125C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.0V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +85C.) (Note 1)
PARAMETER Operating Supply Voltage LEDs Anode Voltage (R0-R7, G0-G7, B0-B7, MUX0, and MUX1) SYMBOL VDD VO fCLKI = 0Hz; CLKO_, DOUT_ loaded 200; calibration DACs set to 0x01 Supply Current IDD fCLKI = 0Hz; CLKO_, DOUT_ loaded 200; calibration DACs set to 0xFF fCLKI = 32MHz; CLKO_, DOUT_ loaded 200; calibration DACs set to 0xFF Input High Voltage LOADI Input Low Voltage LOADI Differential Input Voltage Range CLKI_, DIN_ Common-Mode Input Voltage CLKI_, DIN_ Differential Input High Threshold Differential Input Low Threshold Differential Output Voltage CLKO_, DOUT_ Differential Output Offset CLKO_, DOUT_ Input Leakage Current CLKI_, DIN_, LOADI Input Capacitance CLKI_, DIN_, LOADI Output Low Voltage LOADO Output High Voltage LOADO VOLC VOHC ISINK = 5mA ISOURCE = 5mA VDD - 0.5 VIHC VILC VID VCM VDIFFTH VDIFFTL VOD VOS IIH, IIL Termination 200 at receiver _+ and _- inputs Termination 200 at receiver _+ and _- inputs -100 190 1.125 -1 10 0.05 VDD - 0.2 0.25 1.25 0.15 |VID / 2| 8 -8 550 1.375 +1 0.7 x VDD 0.3 x VDD 1.20 2.4 100 CONDITIONS MIN 3.0 TYP MAX 3.6 7 UNITS V V
28 51 54
52 72 77 V V V V mV mV mV V A pF V V mA
2
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24-Output PWM LED Drivers for Message Boards MAX6974/MAX6975
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +85C.) (Note 1)
PARAMETER Output Slew Time LOADO Output Low Voltage MUX_ Open-Circuit Detection Output Voltage Slew Time R0-R7, G0-G7, B0-B7 Full-Scale Port Output Current R0-R7, G0-G7, B0-B7 ISINKFS VOLM VOCD 80% to 20%, load = 50pF, calibration DACs set to 0xFF VDD = 3.3V, VO = 1.2V, calibration DACs set to 0xFF TA = +85C TA = +125C TA = TMIN to TMAX VDD = 3.3V, VO = 1.2V, calibration DACs set to 0xFF ISINK = 30mA (Note 2) TA = +125C (Note 3) TA = +85C TA = -40C (Note 3) 29.4 29.10 28.2 0.5 0.3 0.9 0.3 30 SYMBOL ISINK = 40mA 200 100 30.6 30.90 31.8 1.7 1 3.0 1.15 mA/V 1.5 0.6 1.7 mA/V 2.0 % mA CONDITIONS 20% to 80%, 80% to 20%, load = 10pF MIN TYP 3 0.4 MAX UNITS ns V mV ns
Port-to-Port Current Matching R0-R7, G0-G7, B0-B7
ISINK
Output Load Regulation
IOLR
VDD = 3.3V, VO = 1.2V to 3.0V, TA = +85C calibration DACs set to 0x80, TA = TMIN to TMAX ISINK = 18mA VDD = 3.0 V to 3.6V, VO = 1.2V, TA = +85C calibration DACs set to 0x80, TA = TMIN to TMAX ISINK = 18mA
Output Power-Supply Rejection
IOPSR
TIMING CHARACTERISTICS
(VDD = 3.0V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at 3.3V, TA = +85C.) (Note 1)
PARAMETER CLKI_ Input Frequency CLKI_ Duty Cycle CLKO_ Output Delay DIN_ Setup Time DIN_ Hold Time DOUT_ Output Delay LOADO Output Delay LOADI Hold Time Watchdog Period tPD-CLKO tSU-DIN tHD-DIN tPD-DOUT tPD-LOADO tHD-LOADI When enabled 11 40 125 300 0.5 5 18 21 SYMBOL fCLKI 40 CONDITIONS MIN TYP MAX 33 60 19 UNITS MHz % ns ns ns ns ns ns ms
Note 1: All parameters tested at TA = +85C. Specifications over temperature are guaranteed by design. Note 2: Specification limits apply to devices at the same TA for TA = TMIN to TMAX. Note 3: Guaranteed by design.
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24-Output PWM LED Drivers for Message Boards MAX6974/MAX6975
Typical Operating Characteristics
(VDD = 3.3V, TA = +25C, unless otherwise noted.)
OPERATING CURRENT CONSUMPTION vs. SUPPLY VOLTAGE VDD
MAX6974 toc01
OPERATING CURRENT CONSUMPTION vs. SUPPLY VOLTAGE VDD
fCLKI = 0MHz CALDAC = 0x00 TA = -40C TA = +25C
MAX6974 toc02
55
fCLKI = 32MHz CALDAC = 0xFF TA = -40C TA = +25C
30
53
28
IDD (mA)
49 TA = +125C 47 45 3.0 3.1 3.2 3.3
IDD (mA) TA = +85C
51
26
24 TA = +125C 22 TA = +85C
20 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE VDD (V) SUPPLY VOLTAGE VDD (V)
LED OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
MAX6974 toc03
LED OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
VDD = +3.0V
MAX6974 toc04
35 30 25 ISINK (mA) 20 15 10 5 0 0
TA = -40C
35 30 25 ISINK (mA) 20 15 10 5 0
TA = +85C TA = +25C TA = +125C
VDD = +3.3V
VDD = +3.6V
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
4
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24-Output PWM LED Drivers for Message Boards
Pin Description
PIN 1 2 3 4 5 6 7 8-15 16-23 24, 40 25 26 27 28 29 30 31 32-39 EP NAME MUX0 CLKI+ CLKIDIN+ DINLOADI I.C. R0-R7 G0-G7 VDD LOADO DOUTDOUT+ CLKOCLKO+ MUX1 AGND B7-B0 GND FUNCTION Multiplex 0 Active-Low, Open-Drain Output. Use MUX0 to drive a pnp transistor. PWM and Serial-Interface Noninverting Clock LVDS Input PWM and Serial-Interface Inverting Clock LVDS Input Serial-Interface Noninverting Data LVDS Input Serial-Interface Inverting Data LVDS Input Serial-Interface Load CMOS Input Internally Connected. Connect to GND. Red LED Drive Outputs. R0 to R7 are open-drain, constant-current sinks. Green LED Drive Outputs. G0-G7 are open-drain, constant-current sinks. Positive Supply Voltage. Bypass VDD to GND with a 0.1F ceramic capacitor. Serial-Interface Load CMOS Output Serial-Interface Inverting Data LVDS Output Serial-Interface Noninverting Data LVDS Output PWM and Serial-Interface Inverting Clock LVDS Output PWM and Serial-Interface Noninverting Clock LVDS Output Multiplex 1 Active-Low, Open-Drain Output. Use MUX1 to drive a pnp transistor. Analog Ground. Connect to GND. Blue LED Drive Outputs. B0 to B7 are open-drain, constant-current sinks. Power Ground. Exposed pad on package underside must be connected to GND.
MAX6974/MAX6975
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24-Output PWM LED Drivers for Message Boards MAX6974/MAX6975
MAX6974 Block Diagram
R LED OUTPUTS EXT. PNP R7 R6 R5 R4 R3 R2 R1 R0 G LED OUTPUTS G7 G6 G5 G4 G3 G2 G1 G0 B LED OUTPUTS B7 B6 B5 B4 B3 B2 B1 B0 EXT. PNP
MUX0 OUTPUT
8-BIT R CALDAC
ISET
R LED DRIVERS R7-R0
8-BIT G CALDAC
ISET
G LED DRIVERS G7-G0
8-BIT B CALDAC
ISET B LED DRIVERS B7-B0
MUX1 OUTPUTS
8 PWM COUNTERS SYNC
8 7-BIT GLOBAL-INTENSITY PDM MODULATOR 12-BIT INDIVIDUAL PWM MODULATOR 288
8
8
8
8 24
0/1
7
CALIBRATION DATA LATCH 7
7 288 LOAD OE MUX0 PIXEL PWM OLD DATA LATCH 288 EN CONTROL 288 288 MUX0 PIXEL PWM NEW DATA LATCH LOAD OE 288
GLOBALINTENSITY DATA LATCH
MUX1 PIXEL PWM OLD DATA LATCH 288 MUX1 PIXEL PWM NEW DATA LATCH EN
LOADI SYNC DETECT CLKI DIN 288-BIT DATA SHIFT REGISTER 288 24-BIT NEW HEADER SHIFT REGISTER
LOADO
MAX6974
CLKO D Q1
DOUT
6
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24-Output PWM LED Drivers for Message Boards
MAX6975 Block Diagram
R LED OUTPUTS EXT. PNP R7 R6 R5 R4 R3 R2 R1 R0 G LED OUTPUTS G7 G6 G5 G4 G3 G2 G1 G0 B LED OUTPUTS B7 B6 B5 B4 B3 B2 B1 B0 EXT. PNP
MAX6974/MAX6975
MUX0 OUTPUT
8-BIT R CALDAC
ISET
R LED DRIVERS R7-R0
8-BIT G CALDAC
ISET
G LED DRIVERS G7-G0
8-BIT B CALDAC
ISET B LED DRIVERS B7-B0
MUX1 OUTPUTS
8 PWM COUNTERS SYNC
8 5-BIT GLOBAL-INTENSITY PDM MODULATOR 14-BIT INDIVIDUAL PWM MODULATOR 336
8
8
8
8 24
0/1
5
CALIBRATION DATA LATCH 5
5 336 LOAD OE MUX0 PIXEL PWM OLD DATA LATCH 336 EN CONTROL 336 336 MUX0 PIXEL PWM NEW DATA LATCH LOAD OE 336
GLOBALINTENSITY DATA LATCH
MUX1 PIXEL PWM OLD DATA LATCH 336 MUX1 PIXEL PWM NEW DATA LATCH EN
LOADI SYNC DETECT CLKI DIN 336-BIT DATA SHIFT REGISTER 336 24-BIT NEW HEADER SHIFT REGISTER
LOADO
MAX6975
CLKO D Q1
DOUT
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24-Output PWM LED Drivers for Message Boards MAX6974/MAX6975
Detailed Description
The MAX6974/MAX6975 drive 24 nonmultiplexed LEDs or 48 multiplexed LEDs for various indoor and outdoor display applications. The EZCascade serial interface enables large multidriver display panels to be constructed with interconnected MAX6974/MAX6975 devices (see Figure 1). The drivers provide 12-bit (MAX6974) or 14-bit (MAX6975) individual PWM steps for each LED output. Four to seven global-intensity bits provide additional pulse-density modulation (PDM) intensity control (see Table 1). The MAX6974/MAX6975 provide 19 bits of total current/intensity control range per color per pixel, or 18 bits if multiplexing. The total PWM dynamic range encompasses gamma correction and, if desired, individual LED calibration. LED outputs are grouped in ports (R, G, and B) with eight LED outputs per port. Each port features its own current calibration control DAC (CALDAC) with 0.31% resolution to set the current. The MAX6974/ MAX6975 current calibration feature allows unmatched LEDS from different lots and manufacturers to be color matched.
Power-Up
On power-up, the MAX6974/MAX6975 set the calibration current to the minimum current for all LED outputs and clear the global-intensity PDM data, individual-intensity PWM data, and the timing counters. The display remains blank after CLKI starts running. The watchdog function is inactive after power-up.
HOST MAX6974/ MAX6975 1 CLKO DOUT LOADO CLKI DIN LOADI CLKO DOUT LOADO CLKI DIN LOADI MAX6974/ MAX6975 2 CLKO DOUT LOADO CLKI DIN LOADI MAX6974/ MAX6975 3 CLKO DOUT LOADO CLKI DIN LOADI MAX6974/ MAX6975 N CLKO DOUT LOADO
LOADI DIN CLKI OPTIONAL FEEDBACK
Figure 1. Generic Cascaded Connection Scheme
Table 1. Comparison of MAX6974/MAX6975
PART MAX6974 MAX6975 24 (7V rated) 30mA 6mA to 30mA LED DRIVE OUTPUTS LED DRIVE CURRENT CALIBRATION DAC RANGE GLOBAL PDM DIRECT 7 bits 5 bits 3 bits MULTIPLEXED 6 bits 4 bits 2 bits INDIVIDUAL PWM 12 bits 14 bits
8
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24-Output PWM LED Drivers for Message Boards
LED-Intensity Control
The MAX6974/MAX6975 provide three levels of output current control for LED drive: calibration DACs (CALDACs), global-intensity control, and individualintensity control. The CALDACs set the port output current levels, while the global-intensity and individualintensity controls modulate the output current on/off times, providing a fine-resolution control of average output currents (see Figure 2). The individual-intensity control operates on each output independently to set each individual LED intensity level. The global-intensity controls modulate MAX6974/MAX6975 outputs simultaneously for a uniform brightness control without affecting color. Using a fixed output current level that is modulated only by on/off control leaves the LED color unaffected while precisely controlling intensity. Finally, all outputs can be turned on and off simultaneously by setting or clearing configuration bit D3 (PWM-ON).
Global-Intensity Control
The MAX6974/MAX6975 adjust global and individual intensities over a time period called a frame. One frame requires 2 19 (524,288) periods of CLKI and corresponds to one video-frame time. Video frames generally contain consecutive images displayed rapidly to yield a motion picture display. Running the MAX6974/ MAX6975 at f CLKI = 31.5MHz allows a video-frame update rate of 60fps for full-motion video (see the MAX6974 Video-Frame Timing and MAX6975 VideoFrame Timing sections). The MAX6974/MAX6975 further divide frames into subframes to allow a unique combination of global- and individual-intensity controls. The number of subframes is equal to the number of global-intensity control steps. The MAX6974 uses 128 subframes per frame in nonmultiplexed mode (corresponding to 7-bit globalintensity PDM control) and 64 subframes in multiplexed mode (corresponding to 6-bit global-intensity PDM control). The MAX6975 features 5-, 4-, 3-, and 2-bit global-intensity control to yield 32, 16, 8, and 4 subframes per frame, respectively. The MAX6974/MAX6975 control global intensity by driving subframes on and off. When a subframe is on, it allows the individual PWM intensity control to be driven on the outputs. Subframes that are off do not have any PWM modulation on the outputs.
MAX6974/MAX6975
Calibration DACs
The 8-bit R, G, and B CALDACs set the output current level for all eight outputs in the R, G, and B ports, respectively (see the MAX6974 Block Diagram and MAX6975 Block Diagram). The R CALDAC, G CALDAC, and B CALDAC range from a low of 6mA (0x00) to a maximum of 30mA (0xFF), providing 94A/step of current trimming. The CALDACs are loaded by the serial interface using command 01 (see Table 4). The B CALDAC data is loaded first, followed by the G CALDAC data, and then the R CALDAC data (see the Serial Interface section). The loaded data takes effect immediately.
Individual PWM Control
The MAX6974/MAX6975 further modulate the time that each subframe is ON by a pulse-width modulation
(mA) 100% 30 25
CALDAC CURRENT 30mA MAX
GLOBAL-INTENSITY PDM
INDIVIDUAL-INTENSITY PWM
21.8mA 20 50% 15 10 0% 5 6mA MIN
100% 100%
50% 50%
Rn, Gn, OR Bn IAVE = 10.22mA
0% 0 CALDAC = 169 255 0 GLOBAL 127 = 96
0% 0 Rn, Gn, OR Bn PWM 4095 = 2560
Figure 2. Relationship Among the CALDACs, Global-Intensity, and Individual-Intensity PWM Controls
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24-Output PWM LED Drivers for Message Boards MAX6974/MAX6975
(PWM) value. Each output current driver in the R, G, and B ports has a unique 12-bit (MAX6974) or 14-bit (MAX6975) PWM control value providing fine resolution adjustment of average current output. Each bit time of the PWM corresponds to one period of CLKI (TCLKI). The PWM setting determines the amount of time, out of the total period, that the output is on. The subframes have PWM off-zones at the start (t SPWM ) and end (tEPWM) of the PWM period (see Figure 3). The subframe period and PWM off zones are shown in Table 2 for each device. The MAX6974 subdivides each subframe by 4096 (12-bit) PWM steps and has 16 cycle off zones, leaving an active PWM region of 4064 PWM steps ranging from 16 to 4079. The MAX6975 subdivides each subframe by 16,384 (14-bit) PWM steps and has 32 cycle off zones, leaving an active PWM region of 16,320 PWM steps ranging from 32 to 16,351. The PWM phase for outputs R0, R2, R4, R6, G0, G2, G4, G6, B0, B2, B4, and B6 use phasing with the outputs on first and off second. Inverse phasing is used for outputs R1, R3, R5, R7, G1, G3, G5, G7, B1, B3, B5, and B7 as shown in Figure 3 to balance the timing of loads on the LED anode power supply. In multiplexed operation, the subframes are shared between MUX0 and MUX1 active times, effectively reducing the number of subframes by 2.
Table 2. Subframe and PWM Timing
PART MAX6974 MAX6975 SUBFRAME (TCLKI) 4096 16,384 tSPWM (TCLKI) 16 32 tEPWM (TCLKI) 16 32 tEMUX (TCLKI) 16 32
LED-Intensity Control Example The three levels of intensity control are shown in Figure 2 for one LED output driver in a MAX6974 in nonmultiplexed mode. As an example, the CALDAC is set to 169DEC, setting the port output current level to 21.8mA. The global-intensity PDM value is set to 96DEC, producing an even distribution of ON subframes out of the 128
MULTIPLEXED SUBFRAME (n), MUX0 tEMUX MUX0
SUBFRAME (n), MUX1
tEMUX MUX1
tSPWM R0, R2, R4, R6 G0, G2, G4, G6 B0, B2, B4, B6 50% ON/OFF PHASING R1, R3, R5, R7 G1, G3, G5, G7 B1, B3, B5, B7 OFF/ON PHASING
tSPWM 75% tSPWM 25% 100% tEPWM
NONMULTIPLEXED SUBFRAME (n) tSPWM R0, R2, R4, R6 G0, G2, G4, G6 B0, B2, B4, B6 75% ON/OFF PHASING R1, R3, R5, R7 G1, G3, G5, G7 B1, B3, B5, B7 tEPWM
SUBFRAME (n + 1)
75%
75% OFF/ON PHASING
75%
Figure 3. Multiplexed and Nonmultiplexed Output Driver Phasing and Example PWM Values
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24-Output PWM LED Drivers for Message Boards
possible (shown in Figure 4 as subframes 1, 3, 4, 5, etc). Each subframe can be ON for a PWM duration set by the individual PWM value. The PWM value setting of 2560DEC out of 4096 (12-bit) results in a further reduction of current ON time (shown in bold trace). The internal PDM logic spreads the on subframes as evenly as possible among the off subframes to keep the effective scanning frequency high. For applications with a slower clock speed, the MAX6975 can increase the display refresh rate by a factor of four to eliminate visible flicker. Setting configuration bit D4 (GLB4) to 1 activates the increased refresh rate (see Table 6). The increased refresh rate reduces the number of global-intensity settings by a factor of four (see Table 3). subframes) to obtain the required number of clock cycles (524,288) per video frame. The MAX6974 requires 36 bits (12 bits per color multiplied by three colors) to drive an RGB pixel. The maximum pixel data that the MAX6974 can send per video frame is 524,288 / 36 or 14,563 pixels, corresponding to 1820 cascaded MAX6974s.
MAX6974/MAX6975
MAX6975 Video-Frame Timing
The MAX6975 also supports up to 60 video frames per second (fps). The following equation shows the required clock frequency to support 60 video fps: 60 (video fps) x 16,384 (clocks per 14-bit PWM period) x 32 (global-intensity subframes) = 31.5MHz. The MAX6975 supports up to a 33MHz clock signal (~63fps). Each 14-bit PWM period contains 16,384 clock cycles; multiply 16,384 by 32 (global-intensity subframes) to obtain the required number of clock cycles (524,288) per video frame. The MAX6975 requires 42 bits (14 bits per color multiplied by three colors) to drive an RGB pixel. The maximum pixel data that the MAX6975 can send per video frame is 524,288 / 42 or 12,483 pixels, corresponding to 1560 cascaded MAX6975s.
MAX6974 Video-Frame Timing
The MAX6974 supports up to 60 video frames per second (fps). The following equation shows the required clock frequency to support 60 video fps: 60 (video fps) x 4096 (clocks per 12-bit PWM period) x 128 (global-intensity subframes) = 31.5MHz. The MAX6974 supports up to a 33MHz clock signal (~63fps). Each 12-bit PWM period contains 4096 clock cycles; multiply that number by 128 (number of global-intensity
Multiplexed vs. Nonmultiplexed Operation
The MAX6974/MAX6975 can double the number of LEDs driven from 24 to 48 through multiplexing. When multiplexing, the two outputs, MUX0 and MUX1, drive
(mA) 30mA MAX 25 169d = 20 15 10 PWM = 2560/4096 OUTPUT LED CURRENT GLOBAL PDM = 96/128 SUBFRAMES
CALDAC CURRENT
6mA MIN 5 ON 0 1 2 ON 3 ON 4 ON 5 6 ON 7 ON 8 ON 9 10 ON 11
SUBFRAME NUMBER ONE FRAME IS 219 (524,288) CLKI CYCLES LONG
Figure 4. The three levels of LED current control (CALDAC, global-intensity PDM, and individual PWM) modulate the average output current.
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24-Output PWM LED Drivers for Message Boards MAX6974/MAX6975
two external pnp transistors, such as FMMTL717, used as common-anode power switches (see Figure 5). Setting configuration bit D0 to 1 enables multiplex
R2 180 C1 120pF
operation. MUX0 and MUX1 alternate the LED anode drive voltage between two sets of LEDs. The R, G, and B ports provide individual PWM control during alternate
+5.55V
Q2 FMMTL717
(BLUES)
R1 560
(BLUES)
ONE COMPLETE 524,288 CLOCK CYCLE MULTIPLEXED VIDEO FRAME (REDS) R1 560 MUX0 C1 120pF MUX1 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 B0 B1 B2 B3 B4 B5 B6 B7
(GREENS)
(GREENS)
(REDS)
Q1 FMMTL717
Figure 5. MAX6975 Multiplexing Two Sets of Eight RGB Pixels with a Single LED Supply and Subframe Timing
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R2 180
SUBFRAME 15 MUX1 16,384 CLKs
SUBFRAME 0 MUX0 16,384 CLKs
SUBFRAME 0 MUX1 16,384 CLKs
SUBFRAME 1 MUX0 16,384 CLKs
SUBFRAME 1 MUX1 16,384 CLKs
SUBFRAME 14 MUX0 16,384 CLKs
SUBFRAME 14 MUX1 16,384 CLKs
SUBFRAME 15 MUX0 16,384 CLKs
SUBFRAME 15 MUX1 16,384 CLKs
SUBFRAME 0 MUX0 16,384 CLKs
24-Output PWM LED Drivers for Message Boards MAX6974/MAX6975
Table 3. MAX6974/MAX6975 Timing Comparison
PART MAX6974 MAX6975 MUX BIT 0 1 0 1 OPERATION Nonmultiplex Multiplex Nonmultiplex Multiplex PWM RES. 12 bits 14 bits TOTAL CLOCKS PER PWM SUBFRAME 4096 16,384 USEABLE CLOCKS PER PWM SUBFRAME 4064 16,320 MAXIMUM PWM DUTY CYCLE 4064 / 4096 = 99.22% 16,320 / 16,384 = 99.61%
PART
GLB4 BIT X X 0
MUX BIT 0 1 0 1 0 1
OPERATION Nonmultiplex Multiplex Nonmultiplex Multiplex Nonmultiplex Multiplex
GLOBAL PDM RES. 7 bits 6 bits 5 bits 4 bits 3 bits 2 bits
SUBFRAMES PER FRAME 128 64 32 16 8 4
CLOCKS PER FRAME 524,288 524,288 131,072
CLOCK FREQUENCY (MHz) FOR 50fps 26.2144 26.2144 6.5536
CLOCK FREQUENCY (MHz) FOR 60fps 31.45728 31.45728 7.8643
MAX6974
MAX6975 1
MUX cycles as shown in Figure 3. The alternating MUX cycles reduce the global-intensity resolution (the number of subframes) by half, which reduces the average LED current by half.
Watchdog
A selectable watchdog timer monitors serial-interface inputs CLKI, DIN, and LOADI. Enabling the watchdog timer requires that CLKI, DIN, and LOADI toggle at least once every 40ms. If any of these transitions fails to occur, then the individual-intensity PWM data latches clear. This condition effectively blanks the LEDs. Update the individual-intensity PWM data registers to turn the LEDs back on. The watchdog timeout does not affect the calibration or global-intensity data, the clock synchronization, or multiplexed/nonmultiplexed setting. Use the watchdog functionality in safety-critical applications where a blanked display is safer than an incorrect display.
LED open circuit is detected on driver outputs by monitoring for output voltages below 200mV. When an open circuit is detected, the MAX6974/MAX6975 increments a fault counter included in the serial-interface protocol that can be routed back to the host transmitter for diagnostics. Any number of open-circuit LEDS, multiplexed or nonmultiplexed, can be detected, however, only one counter increment occurs per device. The MAX6974/MAX6975 detect die temperatures above TDIE = +165C and disable all output drivers by setting all PWM data to zero. The fault counter in the serial-interface protocol is incremented by one count for each cascaded device with an overtemperature condition. The output drivers are turned back on when the die temperature falls below TDIE = +150C. The fault counter value is distinguished between LED opencircuit and overtemperature conditions by the serialinterface command used at the time of detection (see the Serial Interface section for more details).
LED Open-Circuit and Overtemperature Detection
The MAX6974/MAX6975 feature two fault detection functions: open-circuit LED outputs and overtemperature. An
Commands
The MAX6974/MAX6975 have four commands used to load all operating mode and LED output current data.
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24-Output PWM LED Drivers for Message Boards
Each command is uniquely identified by two bits, C1 and C0, embedded in the serial-interface protocol structure. The commands Load CALDAC, Load GlobalIntensity PDM, and Load Configuration each require 24 bits of data (3 bytes) for every cascaded device. The number of bits required for the command load individual PWM varies by device and multiplex mode of operation. Each cascaded device can receive unique data for CALDACs, global intensity, configuration, and individual PWM output drivers. Generally, all cascaded devices are operated in the same configuration mode. The data bytes are transmitted MSB first for all commands. The commands are communicated to all cascaded devices by the host using the synchronous serial-interface and protocol structure (see the Serial Interface section for details). The four commands and the data lengths for each command are shown in Table 4. The MAX6974, operating in nonmultiplexed mode, requires twenty-four 12-bit individual PWM data (288 bits total) and requires forty-eight 12-bit data (576 bits total) in multiplexed operation mode. Similarly, the MAX6975, operating in nonmultiplexed mode, requires twenty-four 14-bit individual-intensity PWM data (336 bits total) and requires forty-eight 14-bit (672 bits total) data in multiplexed mode. The individual PWM data are
MAX6974/MAX6975
loaded into an intermediate latch and transferred to the actual PWM latches at subframe 0 and PWM clock 0. The R, G, and B calibration DACs are loaded with 8-bit data each in nonmultiplexed and multiplexed modes. Data is updated immediately into the CALDAC latches (see Table 8). The MAX6974/MAX6975 require one data byte to set the global-intensity PDM for all output drivers. The globalintensity PDM data has a variable number of active bits depending on the multiplex operating mode and, for the MAX6975, the global-quarter setting. The number of bits used for global-intensity control is always justified to the LSB of the data byte, as shown in Table 5. One byte of data is sent three times with the global-intensity PDM data bits justified to the LSB. Data is updated into the PWM latches at subframe 0 and PWM clock 0 (see Table 9). When using the MAX6975 5-bit global-intensity setting, the settings range from 0 to 63 to set the global intensity from 1 to 64 subframes ON to 64 out of 64 subframes ON. When using the MAX6974 7-bit global-intensity setting, the settings range from 0 to 127 to set the global intensity from 1 out of 128 subframes ON to 128 out of 128 subframes ON.
Table 4. Commands and Data Length
CMD[1:0] C1 C0 COMMAND DATA LENGTH PER CASCADED DEVICE 288 bits (MAX6974 nonmultiplexed) 0 0 Load individual PWM 576 bits (MAX6974 multiplexed) 336 bits (MAX6975 nonmultiplexed) 672 bits (MAX6975 multiplexed) 0 1 1 1 0 1 Load CALDAC Load global-intensity PDM Load configuration 24 bits 24 bits 24 bits
Table 5. Global-Intensity Data Bit Justification
PART MAX6974 GLB4 X X 0 MAX6975 0 1 1 MUX 0 1 0 1 0 1 TOTAL BITS 7 6 5 4 3 2 MSB D7 0 0 0 0 0 0 D6 Bit[6] 0 0 0 0 0 D5 Bit[5] Bit[5] 0 0 0 0 D4 Bit[4] Bit[4] Bit[4] 0 0 0 D3 Bit[3] Bit[3] Bit[3] Bit[3] 0 0 D2 Bit[2] Bit[2] Bit[2] Bit[2] Bit[2] 0 D1 Bit[1] Bit[1] Bit[1] Bit[1] Bit[1] Bit[1] LSB D0 Bit[0] Bit[0] Bit[0] Bit[0] Bit[0] Bit[0]
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24-Output PWM LED Drivers for Message Boards
The global-intensity data is received in an intermediate register and is applied to the outputs at subframe 0 and PWM clock 0. The MAX6974/MAX6975 have one byte of configuration data with 5 active bit settings as shown in Table 6. One byte of data containing configuration bit settings is sent three times. Data is updated immediately into the CALDAC latches. See Table 10. The loaded configuration settings take effect immediately.
Serial Interface
The MAX6974/MAX6975 feature a fully synchronous and fully buffered serial interface that allows cascading of multiple devices. The serial interface consists of inputs (CLKI, DIN, and LOADI) and outputs (CLKO, DOUT, and LOADO). The MAX6974/MAX6975 can pass different data to each cascaded device without any additional inputs to identify the position of the devices in the cascaded chain.
MAX6974/MAX6975
Table 6. Load Configuration Bit Definitions
CONFIGURATION BIT MSB D7 D6 D5 ACRONYM -- -- -- FUNCTION 0 0 0 Not used Not used Not used DESCRIPTION
D4
GLB4
Enables the reduced global-intensity setting in the MAX6975 when set to 1. When set, the MAX6975 uses eight (or four, if multiplexing) PWM Global quarter subframes. GLB4 is set to 0 as power-on default. Setting bit D4 has no effect in the MAX6974. Enable individual PWMs Turns all individual PWM outputs on when set to 1. Power-on default is PWM-ON set to 0 to disable all current output drivers. PWM-ON can be used to turn all LEDs on or off without affecting the global-intensity or individual PWM settings. Setting CRST to 1 synchronously resets internal counters to 0. This action sets the MAX6974/MAX6975 to subframe 0 of the global-intensity subframe counter and clock 0 of all individual PWM counters. The CRST bit is a nonlatching control function that resets to 0 after the counters are set to 0. Setting WDOG to 1 enables the watchdog timer operation. Power-on default is 0. Setting MUX to 1 turns multiplex mode on. Power-on default is 0.
D3
PWM-ON
D2
CRST
Reset frame and PWM counters Watchdog enable Multiplex enable
D1 LSB D0
WDOG MUX
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24-Output PWM LED Drivers for Message Boards MAX6974/MAX6975
The serial interface uses the continuously running clock, CLKI, to synchronously transfer and latch data (33MHz max). The MAX6974/MAX6975 sample inputs DIN and LOADI on the rising edge of CLKI and update outputs DOUT and LOADO on the rising edge of CLKI. The MAX6974/MAX6975 specifications guarantee that cascaded devices observe setup and hold timing from device to device, making external buffers and clock trees unnecessary, even in very large systems. The high-speed CLKI, CLKO, DIN, and DOUT signals use low-voltage differential signaling (LVDS), and the less frequently changing control signals, LOADI and LOADO, use standard CMOS. The differential signals are generally referred to in unipolar shorthand; for example, the statement "CLKI rising edge" means that CLKI+ is rising, and CLKI- is falling. The MAX6974/MAX6975 use LVDS drivers with differential signaling (300mV nominal logic swing around a +1.2V bias) and cascaded CMOS control signals to minimize signal-path EMI and simplify interface timing and printed-circuit board (PCB) layout. Note the differential inputs for the first driver can be driven from +3.3V CMOS using LVDS level translators, such as the MAX9112 terminated with 110 (see Figure 12). A 25MHz to 33MHz clock frequency is recommended to keep the display refresh rate high. When using the MAX6975 in reduced global-intensity mode (GLB4 = 1 in configuration register), the recommended clock frequency range is 6MHz to 33MHz.
Serial-Interface Protocol Structure The MAX6974/MAX6975 serial interface transfers all data and control functions using a protocol structure consisting of header, data, and optional tail segments transmitted in this sequence. The header and tail
CLKI+
CLKItPD-CLKO CLKO+
CLKOtSU-DIN DIN+ tHD-DIN DINtPD-DOUT DOUT+
DOUTtSU-LOADI LOADI tPD-LOADO LOADO tHD-LOADI
Figure 6. Serial-Interface Timing
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24-Output PWM LED Drivers for Message Boards
segments transfer to all cascaded devices, while the data section reduces in bit length as data transfers through the cascaded devices. When LOADI is low, the MAX6974/MAX6975 continuously monitor DIN for reception of the SYNC pattern (see the Header Segment section). LOADI, internally synchronizes the timing relationship between CLKI and DIN with the LOADI signal. The synchronization pattern must be 0xE8. CMD[5:0] Send command bits C1 and C0 three times in succession. The command bits define how many data bits are received and where the data is loaded. The four commands are:
C1:C0 00 01 10 11 COMMAND Load individual PWM Load CALDAC Load global-intensity PDM Load configuration CMD[5:0] 000000 010101 101010 111111
MAX6974/MAX6975
Header Segment The 24-bit header segment consists of an 8-bit fixed synchronization pattern (SYNC), a 6-bit command pattern (CMD), and a 10-bit counter (CNTR) segment (see Table 7). LOADI must change from low to high within plus or minus one clock cycle of the first command bit. When the SYNC bit pattern 0xE8 is recognized, LOADI is monitored for the rising edge, allowing the device to internally synchronize LOADI to CLKI. The six command bits, CMD[5:0], consist of bits C1 and C0 repeated three times. The four commands used by the MAX6974/ MAX6975 are defined by the two bits, C1 and C0. The counter segment is incremented by one for each cascaded device with an internal fault detected. Use the counter segment to collect fault data across the cascaded chain.
HDR[23:0] Complete 24-bit header segment. SYNC[7:0] Synchronization bit pattern 0xE8 is recognized by the MAX6974/MAX6975 during intervals when LOADI is low. The SYNC bit pattern, followed by the rising edge of
CNTR[9:0] This is the counter for open LED or overtemperature fault conditions. The host sends the header segment with the counter value set to zero. The counter value is incremented one count by each device that detects a fault condition in the cascaded chain. The accumulated count value returns to the host from the last device in the cascade chain. The command determines which fault type is incremented to the counter (see LED Open-Circuit and Overtemperature Detection Counter section): CMD[1:0] = X0 Overtemperature faults counted CMD[1:0] = X1 Open LED faults counted
Table 7. Serial-Interface Header
HDR 23 7 1 22 6 1 21 5 1 20 4 0 19 3 1 18 2 0 17 1 0 16 0 0 15 1 C1 14 0 C0 13 1 C1 12 0 C0 11 1 C1 10 0 C0 9 9 b9 8 8 b8 7 7 b7 6 6 b6 5 5 b5 4 4 b4 3 3 b3 2 2 b2 1 1 b1 0 0 b0 SYNC CMD CNTR
HEADER SYNC 1 LOADI 0 COMMAND COUNTER DATA
DIN
1
1
1
0
1
0
0
0 C1 C0 C1 C0 C1 C0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
CLKI (CONTINUOUS)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Figure 7. Header-Segment Timing
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24-Output PWM LED Drivers for Message Boards MAX6974/MAX6975
Data Segment
The bit length of the data segment received by the MAX6974/MAX6975 is dependent on the command specified in the header. The load CALDAC command has three unique data bytes, while load global-intensity PDM and load configuration each have one byte of data repeated three times. The CALDAC data within the command load CALDAC is sent with B CALDAC data first, followed by G CALDAC data, and then R CALDAC data, as shown in Table 8. The data segment of the load individual PWM command has a variable length depending on specific device and configuration settings. The data is always organized as B driver data first in the order of B7 first to B0 last (MSB first), followed by the G driver data in the same order of G7 to G0 (MSB first), and then the R driver data in the order of R7 to R0 (MSB first).
Tail Segment The MAX6974/MAX6975 allow for an optional string of data bits to be transmitted following all device data bits, which is referred to as the tail segment. The data bits of the tail segment are clocked back to the host, following the header, from the last device in a cascaded chain. The number of bits in the tail segment is optional. The tail carries no device-specific data on DIN, but provides feedback confirmation to the host that all data bits were extracted by all devices in the cascade chain.
Table 8. Serial Format for Load CALDAC
HEADER HDR[23:0] DATA 1 B[7:0] G[7:0] R[7:0] DATA 2 B[7:0] G[7:0] R[7:0] DATA 3 B[7:0] G[7:0] R[7:0] ... ... DATA N B[7:0] G[7:0] R[7:0]
B[7:0] G[7:0] R[7:0] N
8-bit data loaded into port B CALDAC 8-bit data loaded into port G CALDAC 8-bit data loaded into port R CALDAC Number of cascaded devices
Table 9. Serial Format for Load Global-Intensity PDM
HEADER HDR[23:0] DATA 1 D[7:0] D[7:0] D[7:0] DATA 2 D[7:0] D[7:0] D[7:0] DATA 3 D[7:0] D[7:0] D[7:0] ... ... DATA N D[7:0] D[7:0] D[7:0]
D[7:0]
Send the 8-bit data for the global-intensity PDM three times (24 total bits)
Table 10. Serial Format for Load Configuration
HEADER HDR[23:0] DATA 1 D[7:0] D[7:0] D[7:0] DATA 2 D[7:0] D[7:0] D[7:0] DATA 3 D[7:0] D[7:0] D[7:0] ... ... DATA N D[7:0] D[7:0] D[7:0]
D[7:0]
Send the 8-bit configuration data three times (24 total bits)
Table 11. Serial Format for Load Individual PWM (Nonmultiplexed)
HEADER HDR[23:0] DATA 1 B7, B6, ...R0 DATA 2 B7, B6, ...R0 DATA 3 B7, B6, ...R0 ... ... DATA N B7...R0
B_...G_...R_
12-bit (MAX6974) or 14-bit (MAX6975) data each
Table 12. Serial Format for Load Individual PWM (Multiplexed)
HEADER HDR[23:0] DATA 1 B7, B7', B6, B6', ...R0' DATA 2 B7, B7', B6, B6', ...R0' DATA 3 B7, B7', B6, B6', ...R0' ... ... DATA N B7, B7', B6, B6', ...R0'
B_ B_' G_ G_' R_ R_'
18
12-bit (MAX6974) or 14-bit (MAX6975) PWM data for each output B_ during multiplex phase MUX0, MSB first 12-bit (MAX6974) or 14-bit (MAX6975) PWM data for each output B_ during multiplex phase MUX1, MSB first 12-bit (MAX6974) or 14-bit (MAX6975) PWM data for each output G_ during multiplex phase MUX0, MSB first 12-bit (MAX6974) or 14-bit (MAX6975) PWM data for each output G_ during multiplex phase MUX1, MSB first 12-bit (MAX6974) or 14-bit (MAX6975) PWM data for each output R_ during multiplex phase MUX0, MSB first 12-bit (MAX6974) or 14-bit (MAX6975) PWM data for each output R_ during multiplex phase MUX1, MSB first
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24-Output PWM LED Drivers for Message Boards MAX6974/MAX6975
HOST CLK0 D0 LOAD0 MAX6974/MAX6975 1 CLKI DIN LOADI CLKO DOUT LOADO CLK1 D1 LOAD1 MAX6974/MAX6975 2 CLKI DIN LOADI CLKO DOUT LOADO CLK2 D2 LOAD2 MAX6974/MAX6975 3 CLKI DIN LOADI CLKO DOUT LOADO CLK3 D3 LOAD3
CLKO DOUT LOADO LOADI DIN CLKI
Figure 8. Example Showing Three-Device Cascade Connection Scheme with the Interconnecting Nodes Labeled for Clarity
DATA: CALDAC DATA 1 G CALDAC DATA: CALDAC DATA 2 G CALDAC
B CALDAC 1 LOADI 0
G CALDAC
B CALDAC
R CALDAC
DIN
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CLKI (CONTINUOUS)
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Figure 9. Timing Example Showing CALDAC Data Set for the First Two Cascaded Devices
Serial-Interface Cascade Timing
The MAX6974/MAX6975 serial-interface protocol timing is simplified by the guaranteed setup and hold characteristics of the outputs from one device driving the inputs of another. An example of a cascade of three MAX6974/MAX6975 devices is shown in Figure 8.
CLK0 D0 D1 D2 D3 HEADER 1 25 CLOCKS 3 BYTES 1 HEADER 2 25 CLOCKS 3 BYTES 2 3 BYTES 2 HEADER 3 25 CLOCKS 3 BYTES 3 T 3 BYTES 3 3 BYTES 3 HEADER 4 T IDLE IDLE
T IDLE T IDLE
Example of Serial-Interface Cascade Timing
The basic timing of a MAX6974/MAX6975 cascaded chain of three devices demonstrates the principle that applies to any number of cascaded devices. The first device connected to the host transmitter is referenced as 1, and the remaining devices are referenced as 2 and 3. Device 3 outputs connect to the host for communicating diagnostic and fault counter data. The first MAX6974/MAX6975, device 1, receives the header and captures the first set of data bits. The number of captured bits is determined by the command given in the header. A timing example of the data transfer for the Load CALDAC command is shown in Figure 9. Device 1 does not send the captured data out on DOUT. Instead, device 1 sends out a new header 25 clock cycles after the reception of the first header bit on DIN. The data flow on each interconnect node is shown in Figure 10.
Figure 10. Data Cascading Example for 24-Bit Data Words
After capturing the first data set, device 1 transmits all following data segments and the optional tail segment on DOUT, delayed by one CLKI cycle. Device 2 receives the new header from device 1, followed by data that now begins with device 2's data set. Device 2 repeats the same process as described above; capturing the first data set received, appending a new header, and passing all subsequent data out DOUT to the next device 3. Device 3 captures the last data set and transmits a header followed by the tail segment. The last header and tail segments are clocked back into the host receiver. The header received by the host contains the updated fault counter data. The tail data bit pattern can be compared to the tail data originally transmitted by the host for data integrity check.
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24-Output PWM LED Drivers for Message Boards MAX6974/MAX6975
When the MAX6974/MAX6975 send individual-intensity PWM data, the data segment bit length is large due to the 12-bit or 14-bit PWM data for each of the 24 outputs (see Figure 11). The various data segment bit lengths for each of the four commands and different operating modes is shown in Table 4. Data capturing is the same as described above with the header segment outputs and data being delayed by the full length of the data bit stream being captured plus one clock cycle.
D0 D1 D2 D3 H1 DATA 1 PWM 288 BITS 289 CLOCKS DATA 2 PWM 288 BITS DATA 3 PWM 288 BITS T
header and new counter value out DOUT. Regardless of the number of open-circuit outputs on a device, the counter increment is 1. The MAX6974/MAX6975 detect die temperatures above TDIE = +165C and disable all output drivers by setting all PWM data to zero. During an overtemperature event, the MAX6974/MAX6975 increment the counter segment data, CNTR[9:0], received on DIN by 1 before transmitting a header and new counter value out DOUT. The output drivers are allowed to be on when the die temperature falls below TDIE = +150C. When there is no fault detected, the counter data is passed directly to DOUT unaltered.
H2 DATA 2 PWM 288 BITS DATA 3 PWM 288 BITS T 289 CLOCKS H3 DATA 3 PWM 288 BITS T 289 CLOCKS
Applications Information
H4 T
Terminations and PCB Layout
Figure 11. Long (288 Bits) PWM Data Cascading Shown for MAX6974 in Nonmultiplexed Mode
LED Open-Circuit and Overtemperature Detection Counter
The MAX6974/MAX6975 feature LED open-circuit detection and overtemperature detection that use the counter section of the header segment to record detected faults. Using commands 01 or 11 force the counter to record LED open-circuit detection faults. Using commands 00 or 10 force the counter to record overtemperature faults. The MAX6974/MAX6975 detect an open circuit on a driver output by monitoring for output voltages below 200mV. When an open circuit is detected, the MAX6974/ MAX6975 increment the counter segment data, CNTR[9:0], received on DIN by 1 before transmitting a
The MAX6974/MAX6975's layout simplifies cascading multiple devices, as the interface signals flow through from each device. The synchronous and buffered nature of the interface simplifies the board design, but pay attention to signal routing and termination, as with other high-speed logic circuits. Terminate the differential input pairs, CLKI+ and CLKI-, as well as DIN+ and DIN-, with a termination resistor as close as possible to the package. When using the MAX6974/MAX6975 as the signal source, use a 200 termination resistor. When using a level translator or clock retimer as the signal source, use a 110 termination resistor. Route each differential input pair as close parallel tracks with spacing or a GND trace between the track pair and the next signal track to minimize cross-coupling. Track lengths up to a few inches do not require termination-matched tracks (transmission lines).
n MORE DEVICES WITH 200 TERMINATION LOAD DIN HOST 110 MAX9112 CLK DIN2 DO1DO2+ 110 DO2CLKIn-1 CLKODINCLKI+ MAX6974 DOUTCLKO+ 200 CLKIn-2 CLKODINCLKI+ 200 MAX6974 DOUTCLKO+ DIN1 DO1+ LOADI DIN+ LOADO DOUT+ LOADI DIN+ LOADO DOUT+
Figure 12. Typical Cascaded Serial-Interface Termination Circuit
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24-Output PWM LED Drivers for Message Boards
Use the same length interface signal paths, whether differential or CMOS, to ensure a uniform propagation delay for each signal. Example of using an external npn transistor: VDD = 3.3V 5%, IOUT = 30mA, external pass transistor VBE = 0.7V to 1V at 30mA emitter current. For best output current accuracy, design VO to be at least 1.2V: R1(MAX) = (3.15 - 1 - 1.2) / 0.030 = 31.7, so choose R1 = 30.
+3.3V VDD MAX6974 MAX6975 Q1 +3.3V +24V
MAX6974/MAX6975
Power-Supply Considerations
The MAX6974/MAX6975 operate with a power-supply voltage of 3.0V to 3.6V. Bypass the VDD power supply to GND with a 0.1F ceramic capacitor as close as possible to the device pins. If the LED supply is shared with the V DD supply, adequately decouple the V DD supply with bulk capacitance to ensure that the fastrising, high-current LED drive currents do not cause transient dips in VDD.
Driving LEDs from a Supply Higher than 7V
An external npn transistor in a cascode configuration extends the output drive voltage above 7V. The external pass transistor's emitter clamps to a V BE below its base, which is connected to the MAX6974/MAX6975's supply voltage. An optional emitter resistor reduces the voltage drop across the MAX6974/MAX6975's output transistor and effectively takes the dissipation off the device into the resistor. The external transistor's collector current is equal to its emitter current (less a small base current), and the MAX6974/MAX6975 accurately control the emitter current with a constant current sink driver structure.
R1 R0 R1 R2 R3 R4 R5 R6 R7 30mA
GND
Figure 13. External Cascode npn Transistor
Typical Operating Circuit
SYSTEM MAX6974 CLK DATA LOAD CLKI DINI LOADI CLKO DINO LOADO CLKI DINI LOADI MAX6974 CLKO DINO LOADO
8 RGB LEDs R0/G0/B0 R1/G1/B1 R2/G2/B2 R3/G3/B3 R4/G4/B4 R5/G5/B5 R6/G6/B6 R7/G7/B7 R0/G0/B0 R1/G1/B1 R2/G2/B2 R3/G3/B3 R4/G4/B4 R5/G5/B5 R6/G6/B6 R7/G7/B7
Chip Information
PROCESS: BiCMOS
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24-Output PWM LED Drivers for Message Boards MAX6974/MAX6975
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
22
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QFN THIN.EPS
24-Output PWM LED Drivers for Message Boards
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX6974/MAX6975
Revision History
Pages changed at Rev 1: 1, 3, 23 Pages changed at Rev 2: 3, 16, 20, 23
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
(c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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